Field of the Invention
The present disclosure relates to electronic memories, and more specifically, to register arrays that use groups of latches.
Description of Related Art
Conventional scannable register array structures include a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The individual latches operate in scannable groups of latches in test mode, where first latches of the scannable groups of latches are L1 latches, and second latches of the scannable groups of latches are L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a subsequent second clock pulse signal, B, for the L2 latches.
The L2 latches are further configured to selectively receive L1 data therein, upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data. However, this needs a specific test sequence to first shift-out data within the L2 latch. Thus, an additional test clock is required to move the data from the L1 stage to the L2 stage. A second pass of the scan shift is required to have data within L1 be observed at the tester through the scan output. This two pass scan, and the additional test clock between the two scan operation (to move data from L1 to L2) makes this testing not fully compatible with mux-scanning (where a multiplexor is placed at the input of each flip-flop in such a way that all flip-flops can be connected in a shift register for multiplexor selection) and thus less useful with industry standards.
Other register arrays use scannable flip-flops (two latches per memory data bit; one data bit, one test bit). The testing of such register arrays uses existing standard scan techniques where each latch pair (L1/L2) is shifted with each scan cycle, and only the L2 latches are normally visible, because only one of the latches is a test latch and the other is a data latch. In essence, the latch pair operates together as a scannable flop that appears to sequence on the rising edge of CLK, and presents data to the register array scan out pin on the falling edge of CLK. Thus, a scanout sequence will appear to observe the contents of each memory data bit. However, such structures increase the area requirement per bit for the register array, by using two latches for each memory data bit.